ROLE
– Define robust CE architecture, ICDs, dataflow, clocks/resets, power domains, fault handling, safe-mode hooks
– Trade studies for FPGA/SoC choice, storage, and high-speed links
– Own sensor/ROIC electrical interface spec, timing budgets, exposure/control loops, register maps
– Hardware–firmware co-design: clean register maps, test hooks, driver APIs, HIL automation
– Test-as-you-fly mindset: unit tests, stress tests, long-duration soak, and environmental test support
– Lead a team of engineers to achieve the above milestones

REQUIREMENTS
– > 6 years in embedded hardware + FPGA/SoC systems shipping real high-speed products
– Proven ownership: architecture → implementation → debug → validation → release
– DO-254 / aerospace process exposure; EMC pre-compliance and design-for-qualification